1. Field of the Invention
The present invention relates to a method for forming an electrically conductive layer on a chip carrier substrate, such as a printed circuit board substrate, and, more particularly, to a method for forming an electrically conductive layer on a chip carrier substrate having through holes or via holes.
2. Description of the Related Art
To increase the component density of a chip carrier, such as a printed circuit board or a printed circuit card, on which electronic components such as integrated circuit (IC) chips are to be mounted, so-called double face mounting, in which electronic components are mounted on both the upper and lower surfaces of the chip carrier, is now practiced. In double face mounting, a chip carrier substrate is provided with through holes, that is, holes extending through the thickness of the substrate, to establish electrical connections between circuit patterns on opposite surfaces of the substrate.
In a substrate having through holes, the internal surface of each through hole is covered by a conductive layer which extends to the circuit patterns on the opposing upper and lower surfaces of the substrate, whereby the circuit patterns on the two surfaces are electrically connected to each other.
Multilayer chip carrier substrates to which patterned conductive layers (circuitry patterns) are laminated are also used to attain high component densities. Such a multilayer substrate includes, for example, via holes, that is, small holes extending from a conductive layer on the substrate surface to a conductive layer internal to the substrate. In such a substrate, a conductive layer provided on the internal surface of each via hole electrically connects the conductive layer on the substrate surface to the conductive layer in the substrate.
The conductive layer provided on the internal surface of a through hole or via hole is conventionally formed simultaneously and integrally with the conductive layer on the substrate surface by so-called plating, that is, depositing metal such as copper typically through a chemical reaction.
When a conductive layer on a chip carrier substrate is formed by plating, because the diameter of each through hole or via hole is small, the metal-containing solution fails to fully penetrate into the hole, so that the conductive layer formed on the internal surface of the through hole or via hole tends to be thinner than the conductive layer simultaneously formed on the substrate surface.
The thinner conductive layer in the through hole or via hole often includes defects such as pinholes or cracks, leading to an open circuit, which is obviously undesirable in an electrical connection. Therefore, the conductive layer in the through hole or via hole needs to have sufficient thickness to assure a continuous electrical connection. Thus, it is normal practice to extend the plating time so that a sufficient thickness is achieved for the conductive layer in the through hole or via hole to avoid pinholes or cracks.
However, when the plating time is extended, not only is the thickness of the conductive layer in the through hole or via hole increased, but the conductive layer on the substrate surface becomes undesirably thick, leading to the following problem. For a substrate with through holes, for example, as shown in FIG. 21, the spacing between the circuit lines formed in a conductive layer 200 (which spacing is indicated by reference d in FIG. 21) on the substrate surface is reduced during the etching of these circuit lines into the conductive layer, leading to the occurrence of short circuits between the circuit lines. Similar problems also arise in a substrate with via holes. The reason why such a problem arises is because the etching procedure employed is so-called wet etching, which results in the cross-section of the etched circuit lines being trapezoidal.
If the spacing between the circuit lines in the design (specification) is increased to achieve a predetermined spacing d, then the density of circuit lines is necessarily decreased, which is undesirable. Thus, it is desirable to increase the thickness of the conductive layer in the through holes without thickening the conductive layer on the substrate surface.
Regarding prior attempts to solve the above problem, Japanese Published Unexamined Patent Application No. 2-174194 discloses a method for thickening metal layers in through holes. According to this method, the surface of a printed circuit board substrate, except for the interior surfaces of the through holes, is coated with a plating resist layer after plating metal onto the substrate surface, including the surfaces of the through holes. Thereafter, because of the presence of the plating resist layer, which prevents plating, metal is plated for a second time onto only the surfaces of the through holes.
When the above-described conventional technique is employed, however, there arises the following problem. In the conventional technique, since the second metal plating is carried out for the substrate with the plating resist layer being present, the plating resist gets mixed into the plating solution, thereby contaminating it, so that uniform plating cannot be attained and defects such as cracks in the plated metal often occur.
In addition to the above problem, the plating solution needs to be filtered over and over to remove contaminants from the plating solution. Furthermore, since plating conditions vary significantly depending upon the existence or absence of the plating resist layer, when the same plating facility is used, different plating conditions need to be established for the first and second platings, which complicates the manufacturing process.
Of course, the first and second platings may be performed in separate plating facilities to avoid contaminating the plating solution. That is, a plating facility dedicated to plating the substrate in the presence of the plating resist layer may be used.